This invention relates in general to telecommunications switching systems, and more particularly to a digital switch for use in a rate conversion application between a very high bandwidth bus and a comparatively low bandwidth bus.
Traditional circuit switching systems utilize a data memory for buffering input signal data and a connection memory for selecting output signal data from within the data memory. Although prior art circuit switch architectures are adequate for xe2x80x9csquarexe2x80x9d systems wherein the bandwidth of the input data stream approximates that of the output data stream, such systems become unwieldy where rate conversion is required between the input and output data streams.
Thus, for example, the input buffer required to ensure no signal loss in a system which converts data from a high speed data bus (such as the H.100 high-bandwidth bus which processes 4096 channels at 8 MHz), and a slower legacy bus architecture (such as the Mitel(copyright) ST-BUS standard which processes 256 channels at 2 MHz), would be 4096 bytes. Furthermore, in an application which supports a constant delay feature (i.e. double-buffered input), then the input memory size doubles to 8192 bytes of SRAM required to store the input data.
Using existing ASIC design techniques, it is estimated that the input data memory size required to implement a prior art digital switch with the above specifications would be as much as xc2xe of the entire ASIC area.
With emerging high bandwidth communications systems, such as those designed according to the Open Telecom Platform (OTP) standard, it is contemplated that rate conversion switching architectures will be in increasing demand as businesses move to interface existing legacy PBX systems to such emerging high bandwidth systems.
According the present invention, a Peripheral Interface Application Specific Integrated Circuit (PASIC) is provided for performing digital switching of a plurality of serial links configured according to the H.100 generic high-bandwidth standard (H.100 is a standard issued by the ECTF (Enterprise Computer Telephony Forumxe2x80x94a telecommunications standards agency) and a further plurality of serial links configured according to the Mitel(copyright) ST-BUS, without requiring a large input buffer. Indeed, according to the present invention, a double-buffered input is provided using only 512 bytes of memory. The substantial reduction in memory buffer size results in significant savings in ASIC die size and cost, when compared to traditional digital switch designs.
Furthermore, according to the preferred embodiment, where a constant delay function is required, the delay buffer is placed in the output path rather than the input path, such that the size of the delay memory is reduced from approximately 4096 bytes according to the prior art, to 512 bytes.